The present invention relates to a D/A conversion circuit and an A/D conversion circuit used as an interface circuit for connecting a digital signal and an analog signal in a semiconductor integrated circuit (LSI).
Recently, LSI circuits have become systematized, and an analog or digital circuit, which was produced from a plurality of chips, has been integrated into a single chip as a system LSI. Such LSI circuits include an A/D conversion circuit or D/A conversion circuit functioning as an interface circuit connecting a digital signal and an analog signal. The operation speed is required to be increased and the control accuracy is required to be enhanced in a system LSI circuit. Therefore, an advanced technique is also required for the interface circuit used therein (A/D conversion circuit and D/A conversion circuit) to perform signal conversion between digital and analog signals at high speed and high accuracy.
FIG. 45 is a circuit diagram showing a conventional D/A conversion circuit 1. The D/A conversion circuit 1 is a resistor string type 4-bit D/A conversion circuit, and a plurality of (sixteen) resistor elements R0 to R15 having the same resistance value are connected in series between a high-potential power supply VRH and a low-potential power supply VRL. Switches SW0 to SW15 are respectively connected to connection nodes of the resistor element R0 to R15 for selectively outputting divided voltages (V0 to V15) of the connection nodes. The outputs of the switches SW0 to SW15 are connected to an output terminal OUT.
The D/A conversion circuit 1 is controlled so that one of the switches SW0 to SW15 is turned on (while the other switches are turned off) in accordance with an input signal (4-bit digital signal), and a predetermined divided voltage is output from the output terminal OUT through the turned-on switch.
In the D/A conversion circuit 1, an analog switch formed by a MOS transistor is used as each of the switches SW0 to SW15. When switching the switches SW0 to SW15 in accordance with the input signal, it is necessary to stabilize (converge) fluctuations in the output voltage associated with the switching by supplying charge to parasitic capacitors C0 to C15 of the switches SW0 to SW15 from the resistor string (the connection nodes of the resistor elements).
Since all of the switches SW0 to SW15 are connected to the output terminal OUT in the conventional D/A conversion circuit 1, the charge transfer amount is equal to the sum of the parasitic capacitors C0 to C15 of the switches SW0 to SW15. Accordingly, the parasitic capacitor (sum of the capacitances C0 to C15) as viewed from the output terminal OUT is large. This poses a problem in that it takes time to charge the parasitic capacitors C0 to C15, and the conversion speed is decreased.
Japanese Laid-Open Patent Publication No. 9-83369 discloses a technique to reduce the parasitic capacitor as viewed from the output terminal OUT and improve the conversion speed in a similar resistor string type D/A conversion circuit as described above. FIG. 46 shows the 3-bit D/A conversion circuit 2 disclosed in the above patent publication. The D/A conversion circuit 2 includes switches SW0 to SW13 forming a tree structure having a plurality of stages (three stages). The D/A conversion circuit 2 is capable of reducing the parasitic capacitor of the switches SW0 to SW13 as viewed from the output terminal OUT and increases the conversion speed. Japanese Laid-Open Patent Publication No. 3-206729 and Japanese Laid-Open Patent Publication No. 55-60333 also disclose D/A conversion circuits having the switches SW0 to SW13 forming a tree structure with a plurality of stages in a similar manner to the D/A conversion circuit 2 shown in FIG. 46.
FIG. 47 is a circuit diagram showing a conventional serial and parallel A/D conversion circuit 3, and FIG. 48 is an explanatory diagram illustrating operation thereof.
The A/D conversion circuit 3 is a 2-bit serial and parallel A/D converter. A plurality of comparators CMP1, CMP2, and CMP3 are used to divide the bits into high-order bits and low-order bits for sequentially performing A/D conversion. In the A/D conversion circuit 3, four resistor elements R21 to R24 having an identical resistance value are connected in series between a high-potential power supply VRH and a low-potential power supply VRL. The comparators CMP1, CMP2, and CMP3 each retrieve an input voltage VIN to compare the input voltage VIN with reference voltages V21, V22, V23 divided by the resistor element string, and output digital signals D0 and D1 in accordance with the comparison results.
More specifically, a first switch SW21 is connected between the resistor elements R21 and R22 for transferring the reference voltage V21, and a second switch SW22 is connected between the resistor elements R23 and R24 for transferring the reference potential V3. The outputs of the switch SW21 and SW22 are connected to each other, and the connection nodes thereof are connected to the comparator CMP2 through the third switch SW23, while being connected to the comparator CMP3 through the fourth switch SW24. The connection nodes of the switches SW21 to SW24 are connected to the low-potential power supply VRL through a capacitor C20. The output terminal of the comparator CMP2 is connected to a fifth switch SW25, while the output terminal of the comparator CMP3 is connected to a sixth switch SW26. The comparator CMP1 retrieves an input voltage VIN to compare the input voltage VIN with the reference voltage V22 between the resistor elements R22 and R23 and outputs a high-order bit signal D1. The comparator CMP2 and CMP3 retrieve the input voltage VIN to compare the input voltage VIN with the reference voltage V21 between the resistor elements R21 and R22 or the reference voltage V23 between the resistor elements R22 and R23 and output a low-order bit signal D0.
The first switch SW21 and the second switch SW22 are complementarily turned on and off by a first selection circuit 4 operating based on the output signal D1 from the comparator CMP1. The third switches SW23 and SW25 and the fourth switches SW24 and SW26 are complementarily turned on and off by a second selection circuit 5 operating based on an external clock CLK.
FIG. 49 is a circuit diagram of the first selection circuit 4, and FIG. 50 is a circuit diagram of the second selection circuit 5 and the comparator CMP1.
As shown in FIG. 49, the first selection circuit 4 includes two inverter circuits 4a and 4b connected in series, and the output signal D1 from the comparator CMP1 is input to the input terminal of the inverter circuit 4a. An output signal from the inverter circuit 4a is provided to the first switch SW21, and an output signal from the inverter circuit 4b is provided to the second switch SW22.
If the input voltage VIN is higher than the reference voltage V22, the output signal D1 from the comparator CMP1 shifts to an H level. In this case, an L level signal is provided to the first switch SW21 from the inverter circuit 4a of the first selection circuit 4, and an H level signal is provided to the second switch SW22 from the inverter circuit 4b. Thus, the first switch SW21 is turned off and the second switch SW22 is turned on. Further, the reference voltage V23 is input to the comparator CMP2 or the comparator CMP3 through the switch SW22. In contrast, if the input voltage VIN is lower than the reference voltage V22, the output signal D1 of the comparator CMP1 shifts to an L level. In this case, an H level signal is provided to the first switch SW21 from the inverter circuit 4a of the first selection circuit 4, and an L level signal is provided to the second switch SW22 from the inverter circuit 4b. Thus, the first switch SW21 is turned on and the second switch SW22 is turned off. Further, the reference voltage V21 is input to the comparator CMP2 or the comparator CMP3 through the switch SW21.
As shown in FIG. 50, the comparator CMP1 is a chopper type comparator including an inverter circuit 7, a capacitor C21, and switches SWA, SWB and SWC. In the comparator CMP1, a first electrode of the capacitor C21 is connected to a first input terminal IN1 via the switch SWA and is connected to a second input terminal IN2 via the switch SWB. A second electrode of the capacitor C21 is connected to an output terminal OUT1 via the inverter circuit 7, and the input and output terminals of the inverter circuit 7 are connected to each other via the switch SWC.
The comparator CMP1 repeatedly performs operations to retrieve the input voltage VIN and to compare the input voltage VIN with the reference voltage V22 based on a clock CLK supplied via the second selection circuit 5.
When the comparator CMP1 retrieves the input voltage VIN, the switch SWA is turned on, the switch SWB is turned off, and the switch SWC is turned on. In the meantime, the capacitor C21 is charged by the input voltage VIN applied thereto via the switch SWA. Since the switch SWC is turned on, the input and output terminals of the inverter circuit 7 are short-circuited so that the input/output voltage of the inverter circuit 7 is reset to a threshold voltage.
Thereafter, when the comparator CMP1 compares the input voltage VIN with the reference voltage V22, the switch SWA is turned off, the switch SWB is turned on, and the switch SWC is turned off. In the meantime, the reference voltage V22 is input to the capacitor C21 via the switch SWB. If the input voltage VIN is higher than the reference voltage V22 (VIN>V22), the voltage input to the inverter circuit 7 via the capacitor C21 becomes lower than the threshold voltage, and the output signal output from the inverter circuit 7 shifts to an H level. In contrast, if the input voltage VIN is lower than the reference voltage V22 (VIN<V22), the voltage input to the inverter circuit 7 via the capacitor C21 becomes higher than the threshold voltage, and the output signal output from the inverter circuit 7 shifts to an L level.
Although not shown, the other comparators CMP2 and CMP3 also have the same circuit configuration as the comparator CMP1 shown in FIG. 50 and operate in accordance with a clock CLK.
The second selection circuit 5 has a plurality of inverter circuits 5a to 5c and a D-type flip-flop circuit (D-FF) 5d. The flip-flop circuit 5d receives, at its clock terminal CK, an inverted signal of the clock CLK through the inverter circuit 5a. The input terminal D of the flip-flop circuit 5d is connected to the inverting output terminal XQ. An output signal output from the output terminal Q of the flip-flop circuit 5d is provided to the switches SW23 and SW25 and also provided to the switches SW24 and SW26 after being inverted by the inverter circuit 5c. Accordingly, the output signal from the flip-flop circuit 5d is changed alternately between an H level and an L level in each cycle of the clock CLK.
When the output signal of the flip-flop circuit 5d is at an H level, the switches SW23 and SW25 are turned on, while the switches SW24 and SW26 are turned off. An output signal D0 according to the result of voltage comparison by the comparator CMP2 is output through the switch SW25. In contrast, when the output signal of the flip-flop circuit 5d is at an L level, the switches SW23 and SW25 are turned off, while the switches SW24 and SW26 are turned on. An output signal D0 according to the result of voltage comparison by the comparator CMP3 is output through the switch SW26.
Operation of the A/D conversion circuit 3 will now be described.
As shown in FIG. 48, the comparator CMP1 repeatedly performs the operation of retrieving the input voltage VIN and the operation of comparing the voltages VIN and V22 in synchronization with the clock CLK. The third switch SW23 (fifth switch SW25) and the fourth switch SW24 (sixth switch SW26) are switched on and off every single period during which the comparator CMP1 performs the retrieval and comparison.
More specifically, the third switch SW23 (fifth switch SW5) is off and the fourth switch SW24 (sixth switch SW26) is on during the period from time t1 to t3. During the period from time t3 to t5, the third switch SW23 (fifth switch SW5) is on and the fourth switch SW24 (sixth switch SW26) is off. Further, during the period from time t5 to t7, the third switch SW23 (fifth switch SW5) is off and the fourth switch SW24 (sixth switch SW26) is on.
During the period from time t1 to t2, the comparators CMP1 and CMP2 retrieve the input voltage VIN having a voltage value equal to that of the high-potential power supply VRH. During the subsequent period from time t2 to t3, the comparator CMP1 compares the input voltage VIN with the reference voltage V22 and outputs an H level signal D1. The comparator CMP2 holds the input voltage VIN retrieved in the previous period (t1 to t2) during the period from time t2 to t3.
At time t3, the first switch SW21 is turned off and the second switch SW22 is turned on by the H level output signal D1 output from the comparator CMP1. Therefore, the reference voltage V23 is input to the comparator CMP2 through the second switch SW22 and the third switch SW23, during the period from time t3 to t5. During this period, the comparator CMP2 compares the input voltage VIN with the reference voltage V23 and outputs an H level signal D0 through the fifth switch SW25.
During the period from time t3 to t4, the comparators CMP1 and CMP3 retrieve the input voltage VIN. In the period from time t4 to t5, the comparator CMP1 compares the input voltage VIN with the reference voltage V22, and outputs an H level signal D1. During this period, the comparator CMP3 holds the input voltage VIN retrieved in the previous period (t3 to t4).
At time t5, the first switch SW21 is kept off and the second switch SW22 is kept on by the H level output signal D1 output from the comparator CMP1. Consequently, the reference voltage V23 is input to the comparator CMP3 through the second switch SW22 and the fourth switch SW24 during the period from time t5 to t7. The comparator CMP3 compares the input voltage VIN with the reference voltage V23 and outputs an H level signal D0 through the sixth switch SW26.
In this manner, the A/D conversion circuit 3 converts a continuous analog signal (input voltage VIN) into 2-bit digital signals D0 and D1 by repeatedly performing the operation as described above.
An A/D conversion circuit designed to output a digital signal by using a hierarchical tree structure including a current mirror circuit for distributing input current has also been proposed (for example, see Japanese Laid-Open Patent Publication No. 7-202698). FIG. 51 is a circuit diagram showing such an A/D conversion circuit 8.
Operation of the A/D conversion circuit 8 will now be described. First, an analog input voltage Vin is voltage-to-current converted by a converter 8a, and the analog current Iin obtained by the conversion is transferred to a first current adder/subtractor circuit 9. Next, the output current from the first current adder/subtractor circuit 9 is transferred to two current adder/subtractor circuits 9. The values of the currents transferred to these two circuits are equivalent to each other. Upon receipt of the current, the two current adder/subtractor circuits 9a and 9b add or subtract different current values to or from the received current value. Each of the currents obtained by the addition or subtraction processing in the two current adder/subtractor circuits 9a and 9b (output currents from the current adder/subtractor circuits 9a and 9b) is transferred to two current adder/subtractor circuits 9aa and 9ab, and 9ba and 9bb and undergoes addition or subtraction processing. Such an addition or subtraction processing is repeated sequentially up to the final-stage current adder/subtractor circuits. It is determined by comparators H1 to H16 whether the outputs of the final-stage current adder/subtractor circuits are high or low. The outputs of the comparators H1 to H16 are converted to a digital code by an encoder circuit 10 and the digital code is output.
FIG. 52 is a conceptual diagram of the A/D conversion circuit 8 shown in FIG. 51. In FIG. 52, each numeric value shown below each branching point indicates the current value that is to be added or subtracted at the branching point.
In the D/A conversion circuit 2 shown in FIG. 46, the switches are connected in a tree structure with a plurality of stages (three stages) so as to reduce the parasitic capacitor of the switches connected to the output terminal OUT. However, the switches in the respective stages are switched in accordance with an input signal. This causes movement of charge in the parasitic capacitor of the switches in accordance with the output voltage. Therefore, it is difficult to shorten the conversion time period.
In the A/D conversion circuit 3 shown in FIG. 47, loss time due to conversion is avoided by continuously operating the comparator CMP1 for converting high-order bits. However, two other comparators CMP2 and CMP3 are required to convert low-order bits. This poses a problem of increase in power consumption.
In the A/D conversion circuit 8 shown in FIG. 51, it is necessary to add or subtract different current values in the two current adder/subtractor circuits 9a and 9b to which current is transferred. Therefore, if a multiple bit configuration is employed as in the A/D conversion circuit 8, circuit blocks with the same configuration cannot be repeatedly arranged. This makes the circuit configuration complicated and induces an error in the relative accuracy between the current adder/subtractor circuits, which in turn deteriorates the A/D conversion accuracy.
When the D/A conversion circuit 1 or 2 or the A/D conversion circuit 3 is incorporated in a semiconductor integrated circuit (LSI) as an interface circuit, the LSI will have problems in increase of operation speed, reduction of power consumption, and improvement in accuracy.
It is an object of the present invention to provide a D/A conversion circuit capable of performing D/A conversion at high speeds. It is also an object of the present invention to provide an A/D conversion circuit capable of reducing the current consumption. Further, it is also an object of the present invention to provide an A/D conversion circuit capable of performing A/D conversion with high accuracy.